Fractional-N PLLs are used in many devices. They are usually included in frequency synthesizers, data recovery components, clock recovery components and the like. Many modern telecommunication device, such as radios include fractional-N PLLs.
The following patents and patent applications, all being incorporated herein by reference, provide a brief overview of some prior art fractional-N PLLs: U.S. Pat. No. 6,603,360 of Kim et al., titled “Phase locked loop circuit for a fractional-N frequency synthesizer”; U.S. Pat. No. 6,553,089 of Huh et al., titled “Fractional-N frequency synthesizer with fractional compensation method”; U.S. patent application publication number 2004/0017261 of Soumyanath et al., titled “Input jitter attenuation in a phase-locked loop”, and PCT patent application publication number WO2004/051855A2 of Beaulaton et al, titled “Arrangement, phase locked loop and method for noise shaping in a phase locked loop”.
FIG. 1 illustrates a prior art fractional-N PLL 10. PLL 10 can generate a synthesized signal Ssynt that has a synthesized frequency Fsynt that is a fractional multiple of a reference frequency Fref of a reference signal Sref. Each synthesized signal is generated by smoothing (or averaging) a sequence that at least two frequency divided signals that have different frequencies. In other words, the frequency divider alters the frequency division ratio and outputs a frequency hopping signal Sdiv. While the loop filter of the PLL averages the frequency hopping sequence to provide the required signal. If, for example, a frequency divider is connected to a K-bit modulator, the sequence includes up to 2K different frequencies.
PLL 10 includes a frequency phase detector that in turn includes a phase detector 11 and a charge pump 12. The charge pump 12 is followed by a loop filter 13 that in turn is followed by a voltage controlled oscillator (VCO) 14.
The VCO 14 generates the output signal of the PLL 10 which is the synthesized signal Ssynt 21. A portion of Ssynt is sent to a feedback loop that includes a frequency divider 15 and a frequency divider modulator 16.
A frequency divided signal Sdiv 22 is sent from the frequency divider 15 to the phase detector 11. This frequency divided signal is also used to clock the frequency divider modulator 16. Sdiv 22 has a frequency of Fdiv. Fdiv=Fsynt/N and N is an the frequency division ratio.
The phase detector 11 receives a stable reference signal Sref 23 having a frequency of Fref, and also receives Sdiv 22. It outputs one or more phase error signals that represents the phase difference between Sdiv 22 and Sref 23. The charge pump 12 receives error signals from the phase detector 11 and generates current pulses representative of the phase difference. The output signal of the charge pump is denoted Scp 24.
These current pulses are provided to the loop filter 13 that in turn performs a smoothing operation to provide a control signal Stune 25 to the VCO 14. The synthesized frequency Fsynt is responsive to the amplitude of Stune 25.
The PLL dynamic, and especially the smoothing characteristics of the loop filter 13 average multiple division ratios to provide a required Fsynt.
There are various types of modulators 16, such as multi modulus dividers and the like. A very common modulator uses sigma delta techniques to perform noise shaping of the noise introduced by the modulator 16. One prior art sigma delta modulator is described in PCT patent application publication number WO2004/051855A2.
A typical charge pump 12 includes a current source, a current sink and multiple switches that connect only one of said current source and current sink to the loop filter 13. The current source, when connected to the loop filter, can pump up the voltage of the loop filter 13. The current sink, when connected to the loop filter 13, can pump down the voltage of the loop filter 13.
A typical prior art phase frequency detector has a dead zone near zero phase difference. Such a detector is not able to properly respond to minor phase differences between Sdiv 22 and Sref 23. If the phase difference between these signals is small the PLL 10 introduces a jitter to Ssynt 21.
In order to reduce the effect of the dead zone various solutions were provided. “A simple precharged CMOS phase frequency detector”, H. Johansson, IEEE Journal of Solid State Circuits, Vol. 55, No. 2, February 1998, which is incorporated herein by reference, and “A 1.1-Ghz CMOS Fractional-N Frequency Synthesizer with 3-b Third-Order ΣΔModulator”, W. Rhee, B. Song and A. Ali, IEEE Journal of Solid State Circuits, Vol. 35, No. 10. October 2000 describe a phase frequency detector that does not have a dead zone in its phase characteristics.
Another solution, very suitable for Frac-N PLLs, involves introducing a fixed trickle current to the charge pump 12. The fixed trickle current generates a fixed phase delay between Sref and Sdiv. Thus, even if the PLL is locked the charge pump is out of the dead zone.
The phase difference introduced by the fixed trickle current must be sufficiently long to allow very linear charge-pump response with regard to Frac-N modulation. If the charge pump operates in a non-linear zone (even for a fraction of the frequency hopping sequence) this non-linearity will turn into a low frequency noise, degrading in-band phase noise performance.
Frequency divider modulator 16 alters the frequency division ratio in synchronization with the pulses of the charge pump. The modulation is characterized by a strong digital activity generating noise that potentially couples in PLL sub-blocks. And disturbs the phase comparison process. In some prior art PLLs, the modulator activity is synchronized with the phase detection, and the generated noise directly affects the charge pump current pulses. The necessary linearity relationship between the Frac-N modulation and the charge pump current injection into the loop filter is then broken, and strong low frequency in-band noise arises on the synthesized signal Ssynt.
In addition, various components, including internal components of the PLL, components that do not belong to the PLL (such as transmitters, modulators, processors, I/O components, and the like) are also clocked by the rising edge or by the failing edge of the reference signal. The operation of such components also disturbs the phase comparison process and adds to the noise of the PLL.
Due to the complexity of modern devices and due to the complexity of noise generating mechanisms the noise characteristics of various systems are hard to predict or simulate. Accordingly, using the clock signal as a trigger to multiple events does not necessarily provide adequate noise suppression.
There is a need to provide a method for noise reduction in a PLL and to provide a device that has noise reduction capabilities.